Since the first one integrated circuit was appeared in 1959, the number of IC chips fabricated on a wafer has been dramatically increased year by year. It is known that the size of each IC chip can be successfully minimized by improving the technique for the IC fabrication. However, when the length of the channel in a MOSFET is shortened, a short-channel effect is accordingly caused because of the occurrence of the phenomena of a two-dimensional potential distribution, a high electrical field conduction, and the generation of the electrical charges within an oxide layer in the MOSFET.
So far as a specific dopant concentration in the channel is concerned, when the size of the MOSFET is reduced, which means that the channel length is correspondingly shortened, two depletion regions formed close to the interface of the source and the drain are possible with each other since the sum of the widths of the two depletion regions is merely approximately equal to the length of the channel, and the potential distribution within the channel is two-dimensional. As a result, the MOSFET will degenerate on the sub-critical characteristic thereof, change the critical voltage thereof due to changes, in the length of the channel and the applied bias, and lose the original function of the transistor because the two depletion regions thereof are interconnected.
Furthermore, owing to the shortening of the channel, the electrical field in the channel increases. The mobility of carriers in the channel increases with the increase of the electrical field until it reaches a saturation value. If the electrical field continuously increases, the amount of the carriers will be multiplied at a region near the drain to result in an effect of parasitic bipolar junction transistor due to the occurrence of the substrate current generated thereby. The increased electrical field will also cause hot carriers to be introduced into the gate oxide and thus results in reliability problems of the charged gate oxide, the continuous shift of the threshold voltage, and the degeneration of the transconductance thereof.
Short-channel effects make the characteristics degeneration and the reliability of the transistor device even worse. In the sub-micron MOSFET manufacturing process, it is required to have a shallow depth for the source or the drain junction of a MOSFET to prevent its depletion regions from mutual punch-through and to eliminate the adverse influences caused by short-channel effect resulting from two-dimensional distribution of the potential.
The formation of the lightly doped drain (LDD) region may be helpful to deal with the above-described situation. Two LDD regions are formed respectively between the source and the channel and between the drain and the channel. The LDD regions are sufficient to reduce the electrical field in the channel to solve the reliability problems caused by the high electrical field conductance effect and by the generation of hot carriers, and to reduce the short-channel effect as well.
Take an n-channel MOSFET for example. The prior manufacturing process for fabricating a MOSFET includes steps of:
(1) preparing a p-type wafer as a substrate 10; PA1 (2) introducing p-type field ions to form a p-type isolation region 11 into the substrate 10 by ion implantation; PA1 (3) growing an field oxide 12 on the p-type isolation region 11; PA1 (4) growing a thin S.sub.i O.sub.2, layer as a gate oxide 13 on the substrate 10 through a thermal oxidation; PA1 (5) depositing a polycrystalline silicon layer on the gate oxide 13; PA1 (6) defining a gate region 14 by a mask; and PA1 (7) etching the polycrystalline silicon other than the masked gate region to obtain a gate 14. The obtained intermediate wafer product having a gate thereon is shown in FIG. 1. PA1 (1) Reduction of the backend thermal budget: PA1 (2) Pre-amorphousrizing the surface of the silicon wafer to reduce the projecting range of the doping ions to be implanted before forming the source and drain: PA1 (3) Forming a source or a drain by solid state diffusion,
After the above-mentioned steps, two LDD regions of the source and the drain are formed on the intermediate wafer product, as shown in FIG. 2. The prior process includes implanting the low concentration n-dopant to form LDD regions 21, as shown in FIG. 2a, through ion implantation, depositing a S.sub.i O.sub.2 layer 22 on the intermediate wafer product by chemical vapor deposition (CVD), as shown in FIG. 2b, anisotropically etching the intermediate wafer product to form a side-wall oxide 23 beside the gate 14, as shown in FIG. 2c, implanting high concentration n-type ions to form a source and a drain 24 with small residual LDD regions 25 formed under the side-wall oxide 23, as shown in FIG. 2d, and depositing a polysilicon metal dielectric (PMD) on the whole wafer. A backend thermal budget (or backend thermal cycle) is also used to planerize the dielectric. Of course, the source, the drain, and two LDD regions are therefore driven much deeper into the wafer, as shown in FIG. 2e.
As what is mentioned above, the prior technique is unaffordable to fabricate a MOSFET having a shallow junction for the source or the drain. Three possible methods for solving this problem are respectively described as follows:
This method is most adopted in the fabrication of the MOSFET. However, if the PMD is planerized by the normal borophosphorous silicate glass (BPSG) reflow procedure, it is limited to reduce the thermal budget and it is improper for this procedure to fabricate a MOSFET having a size of less than 0.35 [t. Another feasible ways are to adopt a deposition process using ozone and tetra ethyl ortho silicate (TEOS), a spin on glass (SOG) process which is a process to uniformly coat a dielectric layer on the wafer in a spinning way, a photoresistor etch back process, or a chemical mechanical polishing (CMP) process. Unfortunately, these processes are either over-expensive or still under development.
This method is impractical because junction leakage always occurs and the depth of the junction for the source or the drain is also affected by the backend thermal budget.
This method is to use a doped polycrystalline silicon, a doped polycide, or a doped silicon dioxide as a diffusion source and make the dopant in the diffusion source be diffused into the source or the drain by a backend thermal budget. A shallow junction of the source or the drain is obtained thereby, and on the other hand, the damage caused by the ion-implantation in the source or drain is avoided. The restriction is that this method can only be used for manufacturing a source or a drain, but it is impossible to form thereby an LDD region. The short-channel effect can be effectively reduced only when the depth of the junction of the LDD region is made shallow. Therefore, this method is not advantageous.